Disha Expert Team Solutions for Chapter: Computer Organization & Architecture, Exercise 1: Exercise
Disha Expert Team Computer Science Solutions for Exercise - Disha Expert Team Solutions for Chapter: Computer Organization & Architecture, Exercise 1: Exercise
Attempt the practice questions on Chapter 6: Computer Organization & Architecture, Exercise 1: Exercise with hints and solutions to strengthen your understanding. Professional Knowledge for IBPS & SBI Specialist IT Officer Exam solutions are prepared by Experienced Embibe Experts.
Questions from Disha Expert Team Solutions for Chapter: Computer Organization & Architecture, Exercise 1: Exercise with Hints & Solutions
Which of the following lists memory types from highest to lowest access speed?
The following are the statements about Reduced Instruction Set Computer (RISC) architectures.
The following are some of the sequences of operations in the instruction cycle, which one is the correct sequence?
Which is the most appropriate match for the items in the first column with the items in the second column?
X. Indirect Addressing.
Y. Indexed Addressing.
Z. Base Register Addressing.
I. Array implementation
II. Writing Relocatable code
III. Passing array as parameter
Match the following
| List I | List II |
| A. Base addressing | (p) Reentrancy |
| B. Indexed addressing | (q) Accumulator |
| C. Stack addressing | (r) Array |
| D. Implied addressing | (s) position independent |
Match the following terms in List I to their work in List II:
| List I | List II |
| A. Cyclic Redundancy | (p) Error correction code |
| B. Serial Communication | (q) Wired-OR |
| C. Open Collector | (r) Error detection |
| D. Hamming Code | (s) RS-232-C |
What is the reason if the data outputs of most ICs of ROM are tri-state outputs?
What are the effects of mixing RAM modules with different speed ratings?
